if { ![info exists ::env(XILINX_PART)] } {
  set ::env(XILINX_PART) "xc6slx25ftg256-2"
}

create_project system . -part $::env(XILINX_PART) -force
set_property design_mode RTL [get_property srcset [current_run]]

source tcl/src_files.tcl

add_files -norecurse $SRC_SYSTEM

set_property top system_top [current_fileset]

update_compile_order -fileset sources_1
set_property steps.xst.args.iob false [get_runs synth_1]

launch_runs -runs synth_1 -jobs 1 
wait_on_run  synth_1

open_run synth_1

write_edif -force system_top.edn
write_verilog -force -mode port system_stub.v
write_verilog -force -mode funcsim system_funcsim.v

quit
